1. Field of the Invention
The present invention relates to a phase correction method and apparatus for a spread spectrum wireless communication receiver.
2. Description of Related Art
In wireless communication systems such as mobile wireless systems and wireless LANs, so-called multi-pass fading is generated since signals transmitted from a base station reach a receiver through multiple propagation paths having different path lengths, and the received signals are not added coherently. The RAKE reception system that uses direct spread spectrum signals is known as an effective countermeasure against such multi-path fading.
FIG. 1 shows an example of the frame structure of transmission data in the case in which the RAKE reception system is employed. In this example the pilot symbol blocks P1, P2, . . . , Pn+1 (collectively referred to as P) and the information symbol blocks I1, I2, . . . , In (collectively referred to as I) are arranged alternately in each frame. The length of each of the pilot symbol blocks P1, P2, . . , Pn+1 is set to L symbols, and a known symbol sequence is transmitted. In addition, a prescribed number of information symbols (for example, 36 symbols) is included in each of the information blocks I1, I2, . . . , In.
FIG. 2 is key components of a mobile station 61 for the wireless communication system. In this drawing, the transmission unit is eliminated for the simplicity of the explanation. A spread spectrum signal is received by the reception antenna 11, transformed into an intermediate frequency signal in the high frequency receiver 12, split into two signals in the distributor 13, and supplied to the multipliers 16 and 17. The oscillator 14 generates a signal (cos .omega.t) having an intermediate frequency. The output from the oscillator 14 is directly supplied to the multiplier 16, and is input to the multiplier 17 via a phase shift circuit 15 which shifts the phase by .pi./2.
The multiplier 16 multiplies an intermediate frequency signal received from the distributor 13 and the oscillation output from the oscillator 14, and outputs a base band signal Ri consisting of an in-phase component (I component) via a low-pass filter 62. The multiplier 17 multiplies the intermediate frequency signal from the distributor 13 and the output (sin ot) of the phase shift circuit 15, and similarly outputs a base band signal Rq consisting of a quadrature component (Q component) via a low-pass filter 64. In this way, the received signal is quadrature-detected.
The base band signals Ri and Rq are input to a complex-type matched filter 18, are multiplied by a PN code sequence generated by a PN code sequence generating circuit 19, and are despread. The in-phase component Si of the despread output and the quadrature component Sq of the despread output are emitted from the matched filter 18 and are input to a delay detection circuit 20, a signal level detector 22, and a phase correction means 24.
The delay detection circuit 20 detects the delay of the despread output Si, Sq and outputs the detected delay to a frame synchronization circuit 21 in which the timing of each frame is detected. The resultant timing signal Cf is supplied to the phase correction means 24. The signal level detector 22 calculates the received signal level from the I component Si of the despread output and the Q component Sq of the despread output. The multi-path selector 23 selects multiple peaks having high signal levels as multiple paths. The output Cm of this multi-path selection circuit 23 is input to the phase correction means 24.
The phase correction means 24 corrects the phase of the received signal corresponding to each of the paths. The phase-corrected output of each of the paths is emitted from the phase correction means 24, is synchronously synthesized in a RAKE synthesizer 25, and is output to an output circuit 26. The output of this output circuit 26 is supplied to a subsequent decision circuit or not like which de-modulates and processes the signal.
FIG. 3 is a block diagram showing an example of the interior structures of the phase correction means 24 and the RAKE synthesizer 25. The despread received signals Si and Sq, which are output from the complex-type matched filter 18, are input into the phase correction means 24. The phase correction means 24 has a selector 30 which selectively outputs the despread received signals Si and Sq to multiple phase correction circuits 31-34, which correspond to the multiple paths, with timings that correspond to each of the multiple paths.
The-timing signal Cf output from the frame synchronization circuit 21 and the signal Cm output from the multi-path selector 23 are supplied to the selector 30 and phase correction circuits 31-34. The timing signal Cf initiates the sampling clock generation and the signal Cm defines the sampling timing measured from the timing signal Cf. Each of the phase correction circuits 31-34 corrects the phase of the despread signal of each of the respective paths. The output of each of the phase correction circuits 31-34 is: (1) input into one of the corresponding delay circuits 35-38; (2) delayed by the corresponding delay time so that the timing of all the outputs will coincide; and (3) input to a synthesis circuit 39.
By this procedure, the phase and timing of the received signals output from multiple paths are synchronized when the received signals output from multiple paths are synthesized. In this way, the paths are diversified.
As shown in FIG. 1, the received signal is composed of alternating pilot symbol blocks P and information symbol blocks I. The phase correction process performed in the phase correction circuits 31-34 uses a correction signal (correction vector) calculated from the phase rotation amount (error vector) of the pilot signal contained in the received pilot symbol block P.
Two methods for performing this phase correction process are known. In the first method, a correction vector is calculated from the pilot symbol blocks P positioned before and after the information symbol block I. In the second method, phases are corrected by a correction vector obtained from the pilot symbol block P positioned before the information block I.
FIG. 4 is a block diagram showing an example of the phase correction circuits 31-34 employed for the above-mentioned first method wherein a correction vector is calculated from two pilot symbol blocks P. The delay means 41 stores the received information symbol blocks I and outputs them with a delay. The phase error extractor 42 extracts and averages the phase errors of the received pilot symbol blocks P positioned before and after the information symbol block I to be processed.
The phase corrector 43 corrects the phase by: (1) calculating a correction signal (correction vector) based on the error signal (error vector) emitted from the phase error extraction means 42; and (2) multiplying the correction vector and the received information symbol block I to be processed that is emitted from the delay means 41.
If a complex valued pilot symbol transmitted from a transmitter is given by (a+j.multidot.b), and a despread reception pilot symbol is represented by (Pi+j.multidot.Pq), the average value of the phase errors in the pilot symbol block P is expressed as follows. ##EQU1##
Here, L represents the number of symbols contained in the pilot symbol block P, and the superscript k represents the number of the pilot symbol.
Since the pilot symbol (a+j.multidot.b) to be transmitted is usually a combination of a =(-1, +1) and b=(-1, +1), the average phase error E of the pilot symbol given by equation (1) can be calculated essentially by only adders.
The average phase error vector of the pilot symbol blocks P positioned on both sides of the information symbol block I that has been calculated in accordance with equation (1) can be represented by equations (2) and (3). EQU E.sup.(1) =E.sup.(1).sub.i +j.multidot.E.sup.(1).sub.q (2) EQU E.sup.(2) =E.sup.(2).sub.i +j.multidot.E.sup.(2).sub.q (3)
Here, E.sup.(1) represents the average error vector of the pilot symbol block P that precedes the information symbol block I to be processed, and E.sup.(2) represents the average error vector of the pilot symbol block P that follows the information symbol block I to be processed.
Next, a correction vector for correcting the phase error of each of the information symbols is defined by the following equation. EQU M=M.sub.i +j.multidot.M.sub.q (4)
This correction vector M can be computed from the following equations. EQU M.sub.i =(E.sup.(1).sub.i +E.sup.(2).sub.i)/2 (5) EQU M.sub.q =(E.sup.(1).sub.q +E.sup.(2).sub.q)/2 (6)
Hence, the correction vector M can also be calculated essentially by using adders alone. Since multipliers need not be used, the circuit structure can be simplified.
By multiplying the conjugate vector of the correction vector M of the equation (4) by the reception vector D of each of the information symbols, the phase error can be corrected.
In this way, the corrected signal vector shown in the following equation can be obtained. EQU D=(D.sub.i +j.multidot.D.sub.q).multidot.(M.sub.i -J.multidot.M.sub.q)=(D.sub.i M.sub.i +D.sub.q M.sub.q)=(D.sub.i M.sub.i +D.sub.q M.sub.q)+J.multidot.(D.sub.q M.sub.i -D.sub.i M.sub.q)(7)
Equations (1) through (7) represent operations on a certain path. In actual practice, multiple paths are received. However, the phase error can be corrected for each of the multiple paths by performing the operations of equations (1) through (7) based on each of the post despread signals.
The RAKE synthesis is performed by carrying out such phase correction process on the signal received through each path, and by synchronously adding the received signals of the paths. Then, the synthesized output expressed by the following equations can be obtained. ##EQU2##
Here, the superscript n (n=1, 2, . . . , N) indicates the path number of each of the paths inside a symbol. For example, N is set to 4.
According to the first method, highly accurate correction can be performed since the phases of the information symbol block I is corrected based on the phase error of the pilot symbol blocks P positioned on both sides of the information symbol block I.
FIG. 5 is the phase correction circuit for performing the aforementioned second method. This method corrects phases using the correction coefficient obtained from the pilot symbol block P positioned before the information symbol block I. The phase error extractor 51 extracts phase errors from the received pilot symbol P and averages the phase errors. The phase corrector 52 multiplies the correction vector, which has been calculated based on the output of the phase error extractor 51, by the information symbol.
In this second method, the correction vector is calculated based on the phase error extracted from the received pilot symbol block P preceding the information symbol block I to be processed. The values calculated from equations (10) and (11) are used for the correction vector M. EQU M.sub.i =E.sup.(1).sub.i (10) EQU M.sub.q =E.sup.(1).sub.q (11)
The second method does not require the delay means that was used in the first method for storing the received information symbol blocks I. Therefor the circuitry can be downsized since the correction vector is calculated using only the received pilot symbol block P preceding the information symbol block I. However, the correction accuracy achievable with the second method is inferior to the correction accuracy achievable with the first method.
As stated, highly accurate signal reception can be achieved by the first method. However, this method requires a delay means for storing information block I of the reception data. As a result, the first method requires a large amount of circuitry. This poses a serious problem in applying the is method to mobile telecommunication equipment and so forth. According to the second method, the circuitry can be reduced. However, the degree of correction accuracy achievable with the second method is lower than that achievable with the first method.